VLSI Architecture for Hierarchical Temporal Memory
نویسندگان
چکیده
A large number of real world applications, such as image recognition and understanding, can still not be performed easily by conventional algorithms in comparison with the human brain. Implementing applications that require such intelligence, might therefore require a different approach, for which Hierarhical Temporal Memory (HTM) seems a promising framework. Currently HTM exists as a software model. However, this software implementation has its performance limitations and a distinct learning and operating mode. This paper proposes a possible architecture for VLSI implementation that also allows learning during normal operation.
منابع مشابه
VLSI design of 1-D DWT architecture with parallel filters
Wavelet transform coding has been drawing much attention because of its ability to decompose images into a hierarchical structure that is suitable for adaptive processing in the transform domain. This paper presents an E$cient VLSI design of one-dimensional direct discrete wavelet transform processor. The proposed architecture computes three DWT stages and uses four parallel "lters. The archite...
متن کاملAn efficient and reconfigurable VLSI architecture for different block matching motion estimation algorithms
| This paper describes a VLSI architecture which can be recon gured to support both Full Search Block{Matching algorithm and 3{step Hierarchical Search Block{Matching algorithm. By using a recon gurable register{ mux array and a parameterizable adder tree, the 2{D array architecture provides e cient real time motion estimation for many video applications. We also propose a memory architecture a...
متن کاملA VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture
Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent vision systems, its VLSI implementation with high performance and low power consumption is required. This paper proposes a VLSI convolutional network architecture using a hybrid approach composed of pulse-width modulation (PWM) and digit...
متن کاملDesign and Analysis of a Reconfigurable Hierarchical Temporal Memory Architecture
Self-learning hardware systems, with high-degree of plasticity, are critical in performing spatio-temporal tasks in next-generation computing systems. To this end, hierarchical temporal memory (HTM) offers time-based online-learning algorithms that store and recall temporal and spatial patterns. In this work, a reconfigurable and scalable HTM architecture is designed with unique pooling realiza...
متن کاملA Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture
Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent vision systems, its VLSI implementation with high performance and low power consumption is required. This paper proposes a convolutional network VLSI architecture using a hybrid approach composed of pulse-width modulation (PWM) and digit...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2008